1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly, to an improved method and apparatus for forming electrical fuses by a photolithographic process using a novel mask structure.
2. Description of Related Art
In fabricating microelectronic semiconductor devices on a wafer substrate or chip, such as of silicon, to form an integrated circuit (IC), various metal layers and insulation layers are deposited in selective sequence. To maximize integration of device components in the available substrate area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are needed for denser packing of components per present day very large scale integration (VLSI), e.g., at sub-micron (below 1 micron, i.e., 1,000 nanometer or 10,000 angstrom) dimensions. Redundancy techniques are used in semiconductor fabrication to provide deliberate duplication of circuit components to decrease the probability of a circuit failure and thus increase circuit reliability. To offset defects that can occur in the circuitry, multiple copies of a given circuit component can be connected in parallel to achieve continued operation upon failure of a particular component. Each such multiple component can be provided with a set of fuses that can be blown to replace a failed component by a duplicate one during fusing operation of redundancy activation, e.g., at final IC chip testing.
Some ICs have conductive links between semiconductor devices that are coupled to fuses that can be laser cut (blown) after fabrication. Thus, in a dynamic random access memory (DRAM) circuit, fuses can protect transistor gate stacks from destruction due to inadvertent build-up charges. After IC fabrication, the fuses can be blown to permit the DRAM circuit to function as if the protective current paths never existed. Also, fuses are used to set the enable bit and the address bits of a redundant array element in a DRAM circuit. To replace a defective main memory array element within a main memory array, a redundant array is provided which has a plurality of fuses in a fuse decoder array. In replacing a defective main memory array element, individual fuses in the fuse array are blown to set their values to either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d as required by the decoder circuit. During operation, the values of the fuses in the fuse array are loaded into the fuse latch array upon power up, and these values then decoded by the fuse decoder circuit during run time. This facilitates replacement of specific failed main memory array elements by specific redundant elements of the redundant array, all by well known techniques.
In particular, high density DRAMs are commonly designed with memory cell redundancy whereby the redundant memory cells avoid loss of an entire memory in the event that a minor number of memory cells fail to function. Redundant memory cell activation is effected by blowing fuses selectively placed throughout the memory. Blowing a set of fuses disables the defective memory cell and enables in its place a redundant working memory cell.
Fuses may also be incorporated in an IC of a semiconductor device module adapted for custom wiring operation, depending on the requirements of the end user. By blowing selective fuses in the circuit, the semiconductor device module can be customized for particular purposes. Fuse blowing is effected by heating the fuse to melt it, and creating an open circuit, e.g., to replace a defective memory cell or other component by a functional cell or different component. The fuse is usually of aluminum, copper or other highly conductive metal or metal alloy, and has a central portion or fuse segment (fuse link) of smaller cross sectional area than its ends (connector terminals) to reduce the energy needed to melt the fuse and create an open circuit condition. The melting (blowing) of fuses can be effected by a laser beam with a controlled beam width. This can result in laser-induced damage to the area beneath the fuse link, mainly due to absorption of laser energy. Alternatively, fuses can be electrically blown by applying a high current thereto for heating the fuse link by electrical power. To enable electrical fusing with voltages below about 10 volts in semiconductor devices, it is important that the cross sectional area reduction from the connector terminals to the electrical fuse segment (fuse link) be as large as possible, preferably greater than 5 or 10. However, the need for such large connector terminals limits the proximity of neighboring fuses. The voltage necessary to activate an electrical fuse is very sensitive to the geometry of the fuse. The shape of the fuse, its linearity, and the size of the connector terminals all impact the voltage needed to blow the fuse. It is, therefore, important that the fuse geometry be optimized.
An electrical fuse is basically an expendable overcurrent protective device having a circuit-opening fusible (meltable) conductive, e.g., metal or metallic material, fuse segment (fuse link) heated and destroyed by passing an overcurrent through it. The overcurrent heats the fuse link beyond the normal level of radiation loss of the generated resistance heat that keeps its temperature below that at which it melts. The fuse link resistance is particularly determined by the material of which it is made, its cross sectional area, its length, and its temperature. Like any electrically conductive wire (and apart from the material of which it is made and its temperature), of the length of a fuse link or connector terminal is doubled, its resistance is also doubled, whereas if its cross sectional area is doubled, its resistance is halved. In short, the resistance of a fuse link or connector terminal is directly proportional to its length and inversely proportional to its cross sectional area.
Some examples of the fabrication of semiconductor devices with fuse arrangements are shown in U.S. Pat. No. 4,635,345, U.S. Pat. No. 5,436,496, U.S. Pat. No. 5,313,424, U.S. Pat. No. 5,420,456, and Japanese Patent Document JA 403124047. The disclosure of these references are incorporated herein by reference.
Electrically activated fuses having tight pitches are well suited for use in semiconductors. However, the prior art has not been able to achieve an optimized electrical fuse design and method of fabrication permitting tight fuse pitches in semiconductor devices while enabling electrical fusing at voltages below about 10 volts, such as during diffusing operation of redundancy activation or custom wiring, i.e., without compromising desired pitch reduction. Moreover, the prior art has not been able to provide a fuse mask for use in lithographic semiconductor fabrication which may produce local areas having widths narrower than the allowed minimum design feature.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a fuse mask for use in lithographic semiconductor fabrication which may produce local areas having widths narrower than the allowed minimum design feature.
It is another object of the present invention to provide a method of making such a fuse.
A further object of the invention is to provide a method of using such a fuse to produce local areas, designed to be blown, having widths narrower than the allowed minimum design feature.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure which comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer.
Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 xcexcm, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.
In another aspect of the present invention, there is provided a method of forming an electrical fuse on a semiconductor structure comprising providing a photolithography mask having a plurality of mask elements thereon adapted to absorb transmission of an energy beam, a first mask element having a configuration conforming substantially to a pattern for a desired electrical fuse, and a second mask element spaced from the first mask element adjacent a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow. There is also provided a semiconductor structure having a resist layer thereon for receiving an image conforming to the electrical fuse pattern. The method then includes passing the energy beam through the photolithography mask and onto the resist layer; exposing the resist layer and creating a latent image of the electrical fuse pattern conforming substantially to the configuration of the first mask element except adjacent the second mask element, wherein the latent image of the electrical fuse pattern has a localized, narrowed width compared to an adjacent region of the latent image; and developing the resist layer and using a pattern created by the latent image on the developed resist layer to form an electrical fuse on a semiconductor structure having a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow conforming to the gap in the mask element.
In a related aspect, the present invention provides a photolithography mask having a plurality of mask elements thereon adapted to absorb transmission of an energy beam, a first mask element having a configuration conforming substantially to a pattern for a desired electrical fuse, and a second mask element spaced from the first mask element adjacent a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow. Upon passing the energy beam through the photolithography mask and onto a resist layer there is created a latent image of the electrical fuse pattern conforming substantially to the configuration of the first mask element except adjacent the second mask element, wherein the latent image of the electrical fuse pattern has a localized, narrowed width compared to an adjacent region of the latent image.
The first mask element preferably creates an exposed latent image having a width less than about 0.25 xcexcm, and the localized, narrowed width of the latent image exposed on the resist layer has a width less than the width of the first mask element. The first mask element provided preferably has a first portion having an edge and a second portion extending outward from the edge of the first portion, and the second mask element is adjacent the first portion edge and the second portion of the first mask element. The first mask portion edge provided extends inward adjacent the second portion. More preferably, the first mask element provided has a first portion having an edge and a second portion having a substantially rectangular configuration with a length and a width less than the length, with the length of the second portion extending outward from the edge of the first portion, and the first mask portion edge curving inward adjacent either side of the second portion. There is also provided a pair of second mask elements adjacent the first portion edge and the second portion of the first mask element on either side of the second portion.
In a further aspect, the present invention provides a method of forming an electrical fuse on a semiconductor structure which initially comprises providing a photolithography mask having a mask element thereon adapted to absorb transmission of an energy beam and having a configuration conforming substantially to a pattern for a desired electrical fuse, the mask element including a gap therein conforming to a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow, and providing a semiconductor structure having a resist layer thereon for receiving an image conforming to the electrical fuse pattern. The method further includes passing the energy beam through the photolithography mask and onto the resist layer; exposing the resist layer and creating a latent image of the electrical fuse pattern conforming substantially to the configuration of the mask element except at the gap in the mask element, the gap creating a continuous region of the latent image having a localized, narrowed width compared to an adjacent region of the latent image; and developing the resist layer and using a pattern created by the latent image on the developed resist layer to form an electrical fuse on a semiconductor structure having a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow conforming to the gap in the mask element.
A related aspect provides a photolithography mask having a mask element thereon adapted to absorb transmission of an energy beam and having a configuration conforming substantially to a pattern for a desired electrical fuse. The mask element includes a gap therein conforming to a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow. Upon passing the energy beam through the photolithography mask and onto a resist layer there is created a latent image of the electrical fuse pattern conforming substantially to the configuration of the mask element except at the gap in the mask element, with the gap creating a continuous region of the latent image having a localized, narrowed width compared to an adjacent region of the latent image.
Preferably, the mask element creates an exposed latent image having a width less than about 0.25 xcexcm, wherein the localized, narrowed width of the latent imaged exposed on the resist layer has a width less than the width of the mask element. The mask element provided may have a pointed end shape adjacent the gap, a curved end shape adjacent the gap, or a combination of such or similar configurations. More preferably, the mask element provided has a first portion having an edge and a second portion having a substantially rectangular configuration with a length and a width less than the length, with the length of the second portion extending outward from the edge of the first portion, and wherein the gap is provided between the first portion edge and the second portion.
In yet another aspect, the present invention provides a method of forming an electrical fuse on a semiconductor structure which initially comprises providing a photolithography mask having a mask element thereon adapted to absorb transmission of an energy beam and having a configuration conforming substantially to a pattern for a desired electrical fuse, the mask element having a substantially constant width except for a narrowed width portion therein conforming to a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow and providing a semiconductor structure having a resist layer thereon for receiving an image conforming to the electrical fuse pattern. The method then includes passing the energy beam through the photolithography mask and onto the resist layer, exposing the resist layer and creating a latent image of the electrical fuse pattern conforming substantially to the configuration of the mask element except at the narrowed width portion, narrowed width portion creating a continuous region of the latent image having a localized, narrowed width compared to an adjacent region of the latent image; and developing the resist layer and using a pattern created by the latent image on the developed resist layer to form an electrical fuse on a semiconductor structure having a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow conforming to the gap in the mask element.
A related aspect of the invention provides a photolithography mask having a mask element thereon adapted to absorb transmission of an energy beam and having a configuration conforming substantially to a pattern for a desired electrical fuse. The mask element has a substantially constant width except for a narrowed width portion therein conforming to a localized narrowed region of the electrical fuse pattern at which the electrical fuse is designed to blow. Upon passing the energy beam through the photolithography mask and onto a resist layer there is created a latent image of the electrical fuse pattern conforming substantially to the configuration of the mask element except at the localized narrowed region, with the localized narrowed region creating a continuous region of the latent image having a localized, narrowed width compared to an adjacent region of the latent image. Preferably, the mask element creates an exposed latent image having a width less than about 0.25 xcexcm, and wherein the localized, narrowed width of the latent imaged exposed on the resist layer has a width less than the width of the mask element.